VTC2012 - A top level integration frontend entry tool
For Verilog/VHDL engineers working in ASIC, FPGA or CPLD field.
VTC 2012 (Topweaver), a GUI-based EDA tool with patented technology, is the most powerful and efficient HDL structural integration tool ever in the world. Users can directly drag wires to connect cell modules in the full function interface, ensuring the work is done correctly and efficiently. The machine generated code style is friendly for human to read, although you need not to read it in most cases.
With VTC2012, you can quickly build the HDL code's framework, by top-down or bottom-up flow, and with the document file.
Feature
- Full mixed bidirectional Verilog and VHDL support
- Automatically instantiate cell modules or entities
- Full function dynamic graphic user interface
- Automatic port connection driven by Smart Link technology
- User defined naming rules for instance and wire
- Bus combination and inout construction
- Generate Verilog/VHDL connection module automatically
- Visually adjustment of HDL code format
- Output formatted file list
- Generate test fixture by Verilog and VHDL
- And more...
VTM2012 - A table based interface editor
VTM is intended to be a table based edit tool for HDL module's interface definition, and unify the process of HDL coding and document writing.
TAD - A digital frequency synthesis tool without PLL/DLL
Topweaver Anydivider (TAD) is a GUI based EDA tool to generate a divided output clock (frequency = Fout) based on an input clock (frequency = Fin), without a DLL/PLL. The waveform of the output clock can be either from automatical calculation or from visual adjustment...Read more
